1. Field of the Invention
The present invention pertains to the field of thermal processes. More particularly, this invention relates to the optimization of thermal reactor or diffusion furnace performance for thermally activated processes.
2. Background
Thermally activated processes typically require highly uniform thermal processing control to achieve maximum efficiency. For example, integrated circuit chips typically comprise a set of layered structures formed on a silicon substrate via thermally activated processes. The layered structures usually include, for example, polysilicon structures, oxide structures, and diffusion regions. Typically, such structures are formed on a silicon wafer substrate in a controlled thermal reactive environment suitable for forming the required structures on the silicon wafers.
Typically, such a controlled reactive environment is provided by a thermal reactor. Such thermal reactors are also referred to as diffusion furnaces. A typical prior thermal reactor includes a quartz jar that contains a set of silicon wafers. Such a thermal reactor usually includes a set of heating elements that surround the quartz jar. The heating elements in such a thermal reactor usually subdivide the thermal reactor into a set of thermal zones. The heating elements for the thermal zones are usually separately controllable.
Prior thermal reactor systems usually include a reactor controller that controls the heating elements of the thermal reactor as well as the pressure and flow rates of reactive gasses in the thermal reactor. Typically, the deposition rate of polysilicon structures and oxide structures and the rate of growth of diffusion regions on the silicon wafers are related to the wafer temperature. As a consequence, prior reactor controllers usually attempt to achieve the desired end of run physical parameters for the structures formed on the silicon wafers by monitoring and adjusting the temperature and gas flows of the thermal reactor during deposition.
Such prior reactor controllers typically monitor the temperature of the thermal reactor via online temperature measurements. Typically, such online temperature measurements are obtained with thermocouples positioned within or near the quartz jar and with thermocouples inserted through the heating elements of the thermal reactor.
In addition, such prior reactor controllers typically employ proportional integral derivative (PID) methods to control the temperature of the silicon wafers. Such PID reactor controllers usually obtain temperature measurements from the thermocouples in the thermal reactor as an indication of the temperature of the silicon wafers in the quartz jar. Typically, such PID reactor controllers adjust heater power control signals to the thermal reactor to maintain a set point temperature according to a predetermined process control recipe.
Unfortunately, such thermocouple measurements provide a reasonable indication of silicon wafer temperatures only after a long stabilization period in the thermal reactor. Such a long thermal reactor stabilization period typically increases the total cycle time for forming structures on the silicon wafers load. Such increased cycle time usually increases the cost of manufacturing integrated circuit chips. Moreover, such a protracted thermal reactor stabilization period becomes an increasingly larger portion of total cycle time as wafer processes evolve that require shorter intervals for formation of structures. Also, such a protracted thermal reactor stabilization period becomes a larger portion of total cycle time as the thermal mass in the thermal reactor increases. Such increased stabilization period also results in unwanted diffusion of dopants creating difficulty in making sub-micron devices.
In addition, such prior PID reactor controllers cannot accurately control the thermal gradients that occur along the major axis of the thermal reactor. As a consequence, silicon wafers located at different positions along the axis of the thermal reactor are exposed to differing temperatures during thermal processing. Moreover, such prior PID reactor controllers cannot accurately control the thermal gradients that occur radially on the silicon wafers. As a result, integrated circuit chips located at differing radial positions on a given silicon wafer are exposed to differing temperatures during thermal processing.
Unfortunately, such differing temperatures during processing causes variations in the end of run physical parameters of the processed wafers. Such variations in end of run wafer parameters typically decreases the overall yield of such a manufacturing process. Moreover, such a decrease in yield increases the overall cost of manufacturing such integrated circuit chips.